1. Field of the Invention
The present invention relates to the high density packaging of semiconductor integrated circuits, and more particularly a structure suitable for use in the packaging of wafer-scale semiconductor IC (namely, integrated circuit) substrates, that is, in the so-called wafer stack packaging, and a method of fabricating the same.
2. Description of the Related Art
An increase in integration density of a semiconductor integrated circuit does not only reduce the volume thereof but also decreases a signal delay time, and thus can greatly improve the performance of the semiconductor integrated circuit.
Further, a wafer-scale IC substrate is required to have a large number of input/output signal electrodes. Accordingly, it is important to provide the signal electrodes not only in the peripheral portion of an upper surface of the substrate where circuit elements are arranged, but also on the lower surface (namely, the back surface) of the substrate. In this case, electrical through holes are indispensable for the electrical connection between the upper and lower surfaces. The formation process of a through hole of this kind usually includes steps of boring a hole through the substrate, and forming a conductive layer on the wall of the hole. Anisotropic etching is a typical one of the methods for boring a hole through a silicon substrate. This method is described in an article entitled "Silicon as a Mechanical Material" by K. E. Petersen (Proceedings of IEEE, Vol. 70, No. 5, 1982).
Further, in order to provide conductors which penetrate through a silicon wafer and serve as members connecting the upper and lower surfaces of the substrate, in the substrate at high distribution density, a method has been devised in which aluminum liquid drops are moved across the silicon substrate by thermal migration so that the substrate is provided with recrystallized regions doped with aluminum at a multiplicity of regions, and such aluminum-doped regions are used as the connecting members. In this method, however, the resistance of each aluminum-doped region is as high as several ohms, and the electrical insulation between aluminum-doped regions is not good, as described in the above-referred article.
The so-called wafer stack structure in which a plurality of wafer-scale silicon substrates each provided with an integrated circuit, that is, wafer-scale IC substrates are stacked, is a very important means capable of enhancing the packing density. In such a structure, a wiring method in which a signal is taken out from an IC substrate in a direction perpendicular thereto and is sent to the next IC substrate in this direction, is the most effective method for reducing the total length of wiring conductors. The above wiring method has been carried out by Grinsberg et al, in such a manner that a metal bridge is formed on a substrate, and the substrate is mechanically connected to another substrate through the bridge. (Refer to an article entitled "A Cellular VLSI Architecture", IEEE Trans. Computer, Vol. C-33, No. 1, 1984, pages 69 through 81). The structure thus obtained includes a plurality of wafer-scale IC substrates which are stacked without paying any attention to the cooling of the substrates, and is effective only for a case where each substrate has a small number of connecting terminals. In a case where large-area substrates each having a large number of connecting terminals are stacked, it is very difficult to keep electrical contact between all corresponding connecting terminals of adjacent substrates, and to dissipate heat generated by integrated circuits.